Chippy
instruction set architecture for isolated, accelerated, and analyzable systems
Chippy is a new CPU architecture and ISA, designed from scratch with no legacy baggage. It treats isolation, acceleration, and analyzability as architectural problems, solved at the ISA boundary, not layered on afterward. Containers and virtual machines are where it shines: what other architectures emulate, Chippy provides natively.
Design goals
- Low-cost isolation
- Sandboxes, containers, and VMs are cheap, nestable hardware constructs.
- A precise compiler target
- No legacy modes; behavior is defined at the ISA boundary, with modern atomics and memory-model semantics that map directly from today's systems languages.
- Architectural security boundaries
- Authority is explicitly granted, tightly scoped, revocable, and narrow enough for formal analysis.
- Accelerator-oriented interfaces
- Work submission, completion, synchronization, and data movement are portable contracts.
- Analyzable real-time behavior
- System operations are bounded, so worst-case guarantees can be engineered.
- Owner sovereignty
- The machine answers to its owner: every key readable and replaceable, no vendor-privileged channels, attestation that serves the owner's verifier only, and free drivers, documentation, and firmware throughout.